jpmschweitzerandClaude Opus 4.8 728c460d36 Raise the DSI bridge FIFO refill threshold for underrun margin ...

Bump raw_buf_almost_empty_thrd 512 -> 1024 right after display start so
the bridge demands a DMA refill with more slack still in the FIFO,
letting it ride out a PSRAM-bus latency spike instead of draining to the
blue underrun colour. Symptom mitigation for the bus-arbitration
starvation; the register isn't otherwise exposed.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LKPbR6DY2JygHbyLjxm7Uu

2026-07-15 18:02:59 +02:00

..

components

Lower DSI lane rate to 720 Mbps to smooth framebuffer reads

2026-07-15 18:02:59 +02:00

main

Raise the DSI bridge FIFO refill threshold for underrun margin

2026-07-15 18:02:59 +02:00

CMakeLists.txt

Ease DSI PSRAM write bursts: bigger inv buffer + half-rate rain

2026-07-15 14:43:32 +02:00

partitions.csv

Phase 5: hands-free "Computer" wake word (esp-sr WakeNet + AFE VAD)

2026-07-15 10:52:41 +02:00

sdkconfig.defaults

Record the esp-hosted PSRAM-mempool famine dead-end

2026-07-15 14:43:55 +02:00