jpmschweitzerandClaude Opus 4.8
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Bump raw_buf_almost_empty_thrd 512 -> 1024 right after display start so the bridge demands a DMA refill with more slack still in the FIFO, letting it ride out a PSRAM-bus latency spike instead of draining to the blue underrun colour. Symptom mitigation for the bus-arbitration starvation; the register isn't otherwise exposed. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_01LKPbR6DY2JygHbyLjxm7Uu