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Lower DSI lane rate to 720 Mbps to smooth framebuffer reads

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The stock 1500 Mbps (the P4 maximum) makes the DSI transmit each line in
a tight burst, so the framebuffer reads are bursty and lose the PSRAM
bus to the Wi-Fi SDIO DMA under load. 720 spreads the read out and
tolerates the contention. Espressif's documented underrun mitigation;
the floor at this pixel clock is ~480 Mbps.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LKPbR6DY2JygHbyLjxm7Uu
This commit is contained in:
jpmschweitzer
2026-07-15 18:02:59 +02:00
co-authored by Claude Opus 4.8
parent d4a9fd7265
commit 88a7f3e9cc
1 changed files with 7 additions and 1 deletions
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firmware/components/esp32_p4_wifi6_touch_lcd_xc/include/bsp/display.h
+7 -1
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@@ -23,7 +23,13 @@
#if CONFIG_BSP_LCD_TYPE_800_800_3_4_INCH
#define BSP_LCD_H_RES (800)
#define BSP_LCD_V_RES (800)
#define BSP_LCD_MIPI_DSI_LANE_BITRATE_MBPS (1500)
/* 720 Mbps, not the stock 1500 (the P4 max): a high DSI lane rate makes the
* framebuffer read bursty (a whole line slammed out fast, then idle), and those
* bursty high-demand reads are what underrun when esp-hosted's Wi-Fi SDIO DMA
* contends for the PSRAM bus. Lowering the lane rate smooths the read so it
* tolerates the contention. Espressif's documented underrun fix. Floor at the
* 40 MHz pixel clock / 2 lanes is ~480 Mbps, so 720 keeps margin. */
#define BSP_LCD_MIPI_DSI_LANE_BITRATE_MBPS (720)
#elif CONFIG_BSP_LCD_TYPE_720_720_4_INCH
#define BSP_LCD_H_RES (720)
#define BSP_LCD_V_RES (720)