jpmschweitzerandClaude Opus 4.8 88a7f3e9cc Lower DSI lane rate to 720 Mbps to smooth framebuffer reads ...

The stock 1500 Mbps (the P4 maximum) makes the DSI transmit each line in
a tight burst, so the framebuffer reads are bursty and lose the PSRAM
bus to the Wi-Fi SDIO DMA under load. 720 spreads the read out and
tolerates the contention. Espressif's documented underrun mitigation;
the floor at this pixel clock is ~480 Mbps.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LKPbR6DY2JygHbyLjxm7Uu

2026-07-15 18:02:59 +02:00

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esp32_p4_wifi6_touch_lcd_xc

Lower DSI lane rate to 720 Mbps to smooth framebuffer reads

2026-07-15 18:02:59 +02:00

esp_hosted

Fork fix: the SDIO wedge is FIXED (esp-hosted-mcu #167)

2026-07-15 09:50:27 +02:00