Raise the DSI bridge FIFO refill threshold for underrun margin

Bump raw_buf_almost_empty_thrd 512 -> 1024 right after display start so
the bridge demands a DMA refill with more slack still in the FIFO,
letting it ride out a PSRAM-bus latency spike instead of draining to the
blue underrun colour. Symptom mitigation for the bus-arbitration
starvation; the register isn't otherwise exposed.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
Claude-Session: https://claude.ai/code/session_01LKPbR6DY2JygHbyLjxm7Uu

firmware/main/desklock_main.c

@@ -16,6 +16,7 @@
 #include "freertos/semphr.h"
 #include "freertos/task.h"
 #include "bsp/esp-bsp.h"
+#include "soc/mipi_dsi_bridge_struct.h"
 
 #include "desklock.h"
 
@@ -255,6 +256,15 @@ void app_main(void)
     };
     disp_cfg.lv_adapter_cfg.task_stack_size = 16 * 1024;
     bsp_display_start_with_config(&disp_cfg);
+
+    /* Raise the DSI bridge FIFO "almost empty" threshold (hardware default 512)
+     * so the bridge demands a DMA refill with more slack still in the FIFO. Under
+     * load, esp-hosted's SDIO DMA bursts win the shared PSRAM bus and briefly stall
+     * the DSI's continuous framebuffer read; a bigger refill margin lets the FIFO
+     * ride out that stall instead of draining to the hardware underrun colour (the
+     * blue flash). Symptom mitigation for the bus-arbitration starvation. */
+    MIPI_DSI_BRIDGE.raw_buf_almost_empty_thrd.dsi_raw_buf_almost_empty_thrd = 1024;
+
     bsp_display_backlight_on();
     face_init();