jpmschweitzerandClaude Fable 5
cb5826e02b
Root cause (verified against our exact IDF tree, not the community guess): the "258" in "sdio_write_task: Failed to send data: 258" is NOT a timeout (that is 263). 258 = 0x102 = ESP_ERR_INVALID_ARG. On the ESP32-P4, block- mode CMD53 writes require the SOURCE buffer to be 64-byte (cache-line) aligned; the IDF sdmmc driver rejects a misaligned source with INVALID_ARG BEFORE any bus activity. esp_hosts write loop then declares "Unrecoverable host sdio state" and reboots the whole P4. The audio TX payload is not 64-aligned, so streaming mic audio wedged on the very FIRST frame (which is exactly what we saw: listening -> instant Failed to send -> reboot). This also explains why buffer/queue/clock/retry tuning all did nothing: the write never reached the bus. And why our symptom was instant, not after ~100 writes (the community block-mode-desync theory) — it is the first misaligned buffer, every time. Fix: vendored esp_hosted 2.12.11 as an editable local component (overrides the registry copy) and bounce a misaligned TX payload through one aligned DMA scratch buffer in hosted_sdio_write_block (port_esp_hosted_host_sdio.c). TX is serialized by the bus lock so a single static bounce buffer is safe; freed in hosted_sdio_deinit. Host-only change — no C6 reflash. VERIFIED ON HARDWARE (autonomous self-test): 40s of continuous mic-audio upstream streaming — the traffic that previously wedged on the first frame — ran clean, zero timeouts, zero reboots. A guarded SDIO_TX_SELFTEST harness is kept (compiled out) for future SDIO stress testing. Credit: root cause + patch designed via multi-agent investigation; the precise 258=INVALID_ARG decode (correcting the upstream community timeout assumption) came from checking our actual esp_err.h. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com>
108 lines
2.4 KiB
Plaintext
108 lines
2.4 KiB
Plaintext
# 1. CPU
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#--------
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CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_120=y
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# 2. BT Configuration
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#---------------------
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CONFIG_BT_ENABLED=n
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CONFIG_BT_CONTROLLER_ONLY=y
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CONFIG_BT_BLUEDROID_ENABLED=
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CONFIG_BT_LE_SLEEP_ENABLE=y
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CONFIG_ESP_HOSTED_CP_BT=n
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# 3.1 BLE over SPI/SDIO
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#-----------------------
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CONFIG_BT_LE_HCI_INTERFACE_USE_RAM=y
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# 3.2 BLE over UART
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#-------------------
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#UART pins, Enable below config, delete sdkconfig and rebuild
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#CONFIG_BT_LE_HCI_INTERFACE_USE_UART=y
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#CONFIG_BT_LE_HCI_UART_FLOWCTRL=n
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#CONFIG_BT_LE_HCI_UART_TX_PIN=5
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#CONFIG_BT_LE_HCI_UART_RX_PIN=18
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# 4. Partition Table
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#--------------------
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CONFIG_PARTITION_TABLE_CUSTOM=y
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CONFIG_PARTITION_TABLE_CUSTOM_FILENAME="partitions.esp32c2.csv"
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# 5. Mempool
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#------------
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CONFIG_ESP_CACHE_MALLOC=y
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# 7. Transport config
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#---------------------
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# CONFIG_ESP_SDIO_NSEND_PSAMPLE=y
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# CONFIG_ESP_SDIO_DEFAULT_SPEED=y
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# CONFIG_ESP_SDIO_STREAMING_MODE=n
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# 8. Wifi config
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#----------------
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CONFIG_WIFI_CMD_BASIC_ONLY=y
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CONFIG_ESP_WIFI_STATIC_RX_BUFFER_NUM=8
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CONFIG_ESP_WIFI_DYNAMIC_RX_BUFFER_NUM=16
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CONFIG_ESP_WIFI_DYNAMIC_TX_BUFFER_NUM=16
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CONFIG_ESP_WIFI_AMPDU_TX_ENABLED=y
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CONFIG_ESP_WIFI_TX_BA_WIN=8
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CONFIG_ESP_WIFI_AMPDU_RX_ENABLED=y
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CONFIG_ESP_WIFI_RX_BA_WIN=8
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CONFIG_ESP_WIFI_RX_IRAM_OPT=y
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CONFIG_ESP_WIFI_IRAM_OPT=y
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# 9. LWIP config
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#----------------
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CONFIG_LWIP_TCP_SND_BUF_DEFAULT=11520
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CONFIG_LWIP_TCP_WND_DEFAULT=11520
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CONFIG_LWIP_TCP_RECVMBOX_SIZE=16
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CONFIG_LWIP_UDP_RECVMBOX_SIZE=16
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CONFIG_LWIP_TCPIP_RECVMBOX_SIZE=32
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CONFIG_LWIP_TCP_SACK_OUT=y
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CONFIG_LWIP_TCPIP_CORE_LOCKING=y
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CONFIG_LWIP_TCPIP_CORE_LOCKING_INPUT=y
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# 10. Optimizations
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#-------------------
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CONFIG_COMPILER_OPTIMIZATION_SIZE=y
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#CONFIG_COMPILER_OPTIMIZATION_PERF=y
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# 11. Stats
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#-----------
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#CONFIG_ESP_HOSTED_FUNCTION_PROFILING=y
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CONFIG_ESP_PKT_STATS=y
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# 12. Priorities
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----------------
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CONFIG_IPERF_TRAFFIC_TASK_PRIORITY=18
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CONFIG_IPERF_REPORT_TASK_PRIORITY=18
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#13. Mem optimizations
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#---------------------
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CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y
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CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ=120
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CONFIG_ESP_DEFAULT_CPU_FREQ_MHZ_120=y
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CONFIG_FREERTOS_UNICORE=y
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#14. C2 specific opts
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#---------------------
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CONFIG_ESPTOOLPY_FLASHSIZE_4MB=n
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CONFIG_ESPTOOLPY_FLASHSIZE_2MB=y
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CONFIG_ESP_DEFAULT_TASK_STACK_SIZE=2048
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CONFIG_C2_C5_MODULE_SUB_BOARD=y
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#15. For C2 26 MHz XTAL chips only
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#---------------------------------
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CONFIG_SOC_XTAL_SUPPORT_26M=y
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CONFIG_XTAL_FREQ_26=y
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